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State machine bus controller providing function and timing parameters to satisfy requirements of asynchronous bus and more than one type of device on the bus
State machine bus controller providing function and timing parameters to satisfy requirements of asynchronous bus and more than one type of device on the bus
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机译:状态机总线控制器提供功能和时序参数,以满足异步总线和总线上一种以上设备的要求
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摘要
A state machine bus controller for interfacing the CPU of a micro- computer based system with memory and I/O device is described. The controller, while capable of interfacing with a bus which is synchronous in nature, can maintain synchronous handshake with more than one type of microprocessor while providing function and timing parameters to satisfy requirements of an asynchronous bus and more than one type of device which reside on the bus.
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