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Execution unit and method for executing performance critical and non- performance critical arithmetic instructions in separate pipelines

机译:在单独的管线中执行性能关键和非性能关键算术指令的执行单元和方法

摘要

A CPU (central processing unit) of a computer that comprises an issue unit and an execution unit. The issue unit selectively issues arithmetic instructions of a predefined arithmetic instruction type as performance critical arithmetic instructions and non-performance critical arithmetic instructions. The execution unit comprises a performance critical pipeline to execute the performance critical arithmetic instructions. The execution unit also comprises a non- performance critical pipeline to execute the non-performance critical arithmetic instructions.
机译:计算机的CPU(中央处理单元),包括发布单元和执行单元。发布单元有选择地发布预定算术指令类型的算术指令作为性能关键算术指令和非性能关键算术指令。执行单元包括执行关键性能的算术指令的关键性能管线。执行单元还包括非性能关键流水线,以执行非性能关键算术指令。

著录项

  • 公开/公告号US5948098A

    专利类型

  • 公开/公告日1999-09-07

    原文格式PDF

  • 申请/专利权人 SUN MICROSYSTEMS INC.;

    申请/专利号US19970885622

  • 发明设计人 GARY R. LAUTERBACH;ARTHUR T. LEUNG;

    申请日1997-06-30

  • 分类号G06F9/00;

  • 国家 US

  • 入库时间 2022-08-22 02:07:24

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