DRAM incorporating self refresh control circuit and system LSI including the DRAM

摘要

A DRAM and a system LSI incorporating the DRAM. The DRAM has a self refresh address control section (11) inputs a control signal to optionally specify a period of a self refresh operation for the DRAM, a self refresh control circuit (7,71) for specifying the period of an address signal to be used for the self refresh operation and for outputting a self cycle signal, and a row address buffer (8) for providing addresses to the memory cell array (10) based on the self cycle signal as a trigger signal.