DRAM INCORPORATING SELF REFRESH CONTROL CIRCUIT AND SYSTEM LSI INCLUDING THE DRAM

摘要

There is a problem that an appropriate refresh cycle cannot be arbitrarily set and power consumption cannot be reduced.;Self-refresh control circuits 7 and 71 for inputting a control signal for arbitrarily specifying the self-refresh cycle, setting the period of the self-refresh address, and outputting a self-cycle signal, and a self-cycle signal. A self refresh control circuit having a row address buffer 8 for outputting an address to a memory cell array with a trigger is provided.