Non-volatile memory manufacturing method that combines the standard CMOS process EPROM

摘要

(57) [Abstract] The present invention provides a method of incorporating a CMOS standard process and (EEPROM or) EPROM. After grown to (9) the gate oxide film is deposited (10) (hereinafter referred to as poly I) amorphous silicon layer or a polycrystalline doped lightly. In this layer, while the floating gate of the memory cell (13) is defined, the surface is coated with poly-I is in the memory matrix outside. Then, implantation of the source / drain of the memory cell is performed. (10) is masked in order to withstand the injection of high concentration (11) mask poly layer which is located outside of the memory matrix. The formation of the second poly layer is possible, the control gate of the memory cell is formed on the basis thereof. The second poly layer forms a coherent layer with poly I present in the matrix outside. In the sequence of steps in the subsequent standard CMOS process, p-channel MOST and the n-channel MOST is formed. n-type gate of the n-channel MOST p-type gate of the p-channel MOST (22) and (23) is formed from the poly I layer.