SUPERSCALAR MICROPROCESSOR INSTRUCTION PIPELINE INCLUDING INSTRUCTION DISPATCHING AND KILL CONTROL

摘要

An apparatus and method for providing a fast and efficient pipeline in asuperscalar microprocessor having a multiple implementation is provided.Thepipeline of the present invention quickly matches instructions to be dispatched ina pipeline with available resources. Exceptions occurring in the pipeline areprocessed efficiently, all in the same pipeline stage, in a uniform manner. The method comprises predecoding a fetched instruction prior to the fetchedinstruction being advanced to the instruction decode stage by appending a firstfield and a second field to the fetched instruction wherein the first field includesresource information extracted from the fetched instruction and the second fieldincludes a resource categorization field identifying a class of resources used byinstructions of a type similar to the fetched instruction; and furthermore dispatching the fetched instruction after advancing it to the instructiondecode stage to produce a decoded instruction, the dispatching step using thefirst field and the second field to route the decoded instruction to a functionalunit for processing.