Phase difference recovery circuit and phase difference recovery method

摘要

A phase difference recovery circuit and a phase difference recovery method are disclosed. The phase difference recovery circuit 11 of the present invention generates two output signals RCLK and MCLK2 in synchronization with the reference clock signal Rxclk. RCLK is a signal for receiving data of the input pipeline 15 and synchronizing the operation of the interface logic 13. MCLK2 is a signal having the same phase as RCLK, and is a signal generated by delaying MCLK1 generated by the input-only delay lock-loop (RDLL) 17 in the delay unit 19. The MCLK2 operates in response to the reference clock signal Rxclk not only in the active mode but also in the standby mode to synchronize the input pipeline 15. MCLK2 is also fed back into RDLL 17 and acts as a locking reference signal for RDLL 17. And the delay unit 19 has an externally adjustable delay time. Preferably, the delay unit 19 has a laser fuse or an externally controlled RC delay unit.