Phase difference recovery circuit and phase difference recovery method

摘要

A phase difference between clock signals in an integrated circuit is determined after the integrated circuit is packaged. The phase difference can thereby be adjusted so that the effect of the unequal loading on the clock signal timing may be reduced. Determining the phase difference after the integrated circuit is packaged may reduce the cost of fabricating the integrated circuit by reducing the amount of compensation which may need to be performed during the fabrication process. The phase difference may be provided by a selection circuit which can include at least one fuse that is cut by a laser or an RC circuit controlled by a voltage level applied to at least one pin of the integrated circuit. The phase may be adjusted as described above in input pipelines that receive data, output pipelines that output data from the integrated circuit, and in interface circuits that control operation of the integrated circuit.