STRUCTURE AND METHOD FOR SDRAM DYNAMIC SELF REFRESH ENTRY AND EXIT USING JTAG

摘要

The JTAG test logic and memory controller put the SDRAM in self-refresh mode before starting JTAG testing. The memory controller can complete the current memory access or prepare for a JTAG test. During the JTAG test, the SDRAM's self refresh mode maintains data without the need for a clock signal or a refresh signal that is suspended during the JTAG test. Thus, after the JTAG test, the circuit operation can continue without reinitializing the data in the SDRAM.