SCRAMBLING CIRCUIT FOR PATTERN INDUCED JITTER SUPPRESSION IN SDH REPEATER CHAIN

摘要

PURPOSE: A scrambling circuit for reducing pattern-induced jitter in SDH(synchronous digital hierarchy) is provided to increase reliability of long haul transmission by preventing repetition of identical patterns. CONSTITUTION: An initiation timing generator(210) generates an initiation timing signal responding to a frame synchronization signal(FS). An inital value generator(240) generates random initial values for each regeneration repeater to prevent accumulation of pattern-induced jitters. A PRBS(pseudo random binary signal) generator(220) a PRBS corresponding to each random initial value. An initial value inserter(250) inserts the random initial values on a synchronous transfer mode frame by receiving the random initial values.