Auto-lock circuit guaranteeing low jitter in phase-locked loop frequency synthesizers irrespective of process variations

摘要

By using a bias switch (260) to define a unique current range in a bias generator (142) for each n-bit counter output state, it is possible to control a VCO (140) which has a very wide operating frequency range. These frequency ranges must overlap to guarantee the lock irrespective of process or environmental (temperature and voltage) variations. Depending on an input value of an overall lock signal OLS to an n-bit counter (250) at the rising edge of its clock signal CLK, it is possible to scan the full spectrum of VCO frequency ranges until the lock is achieved. By comparing a switch voltage to a reference voltage Vref, it is possible to prevent the PLL from locking at the very right-hand edge of a frequency range unless it can maintain that the lock over the entire operating temperature range. By strobing a fine lock signal FLS at an integer m ( 1) number of points, it is possible to prevent false lock from occurring.