Transistor with ultra short length defined partially by sidewall oxidation of a gate conductor overlying the channel length

摘要

An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length. A mask is formed, from a material resistant to oxidation, upon a conductive gate layer and portions of the conductive gate layer are oxidized to form a gate conductor laterally disposed between a pair of oxide regions. As a result, the gate conductor has an ultra narrow lateral dimension. Source and drain impurity areas are formed self-aligned with sidewall surfaces of the oxide regions. In an embodiment, the oxide regions are removed and lightly doped drain regions are formed self-aligned with sidewall surfaces of the gate conductor. Following LDD formation, the mask is removed, spacers are formed laterally adjacent the gate conductor sidewall surfaces, and a metal silicide is formed upon upper surfaces of the gate conductor and the source and drain impurity areas. In an alternative embodiment, following formation of the source and drain impurity areas, the mask is removed and the oxide regions are etched to form sidewall spacers adjacent the gate conductor. Lightly doped drain implant areas are then formed self-aligned to sidewall surfaces of the gate conductor, and a metal silicide is formed upon upper surfaces of the gate conductor and the source and drain impurity areas.