Method of design for testability, method of design for avoiding bus error and integrated circuit

摘要

The invention provides a method of design for testability of a fault in a portion difficult to test such as an enable input of a tristate element. With regard to an integrated circuit design by a scan path method, an observation circuit including an EXOR tree having inputs in the number equal to that of tristate elements to be designed for testability and an observation dedicated scan FF is disposed. The enable inputs of the tristate elements are connected with the input terminals of the EXOR tree, and the output terminal of the EXOR tree is connected with the ordinary data input terminal of the observation dedicated scan FF. Furthermore, the observation scan FF is inserted into a scan chain already formed by the scan path method. In this manner, a fault in logic circuits for controlling the enable input of the tristate elements, which are conventionally difficult to be detected, can be observed at an external output pin through the scan chain.