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Method to back annotate programmable logic device design files based on timing information of a target technology
Method to back annotate programmable logic device design files based on timing information of a target technology
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机译:基于目标技术的时序信息对可编程逻辑器件设计文件进行批注的方法
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摘要
One embodiment of the invention allows a designer to quickly and efficiently obtain a simulation model for a new integrated circuit implementation of a circuit design from the PLD simulation model for that circuit design. The designer begins with the simulation model of the PLD and back annotates the simulation model with timing characteristics from a target technology. The back annotation substitutes timing values in the PLD simulation model with timing values from the target technology to generate the new integrated circuit simulation model.
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