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Error correction scheme for an integrated L2 cache
Error correction scheme for an integrated L2 cache
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机译:集成二级缓存的纠错方案
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摘要
A multi-way, set-associative cache utilizes a single ECC code in which the ECC bits are evenly distributed among the tag arrays to protect all of the multi-way tags. The cache includes a plurality of data arrays--one for each way of the cache--along with a corresponding plurality of tag arrays. The ECC bits are appended to each tag entry for one of the multiple ways. A single ECC logic block is shared by the tag arrays to detect tag errors. Additional comparator logic is coupled to the tag arrays to perform tag matching.
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