Digital signal processor for detecting out-of-sync and jitter from two clock signals and controlling the interpolation based on deviation and jitter amount

摘要

Buffers 101 and 103 are provided in an input and an output of a signal processing circuit 102 for performing a data transformation between a first digital data signal and a second digital data signal, respectively, and data of one of the first and second digital data signals is interpolated by a data interpolation circuit 106 on the basis of a deviation between sampling frequencies of the first and second digital data signals detected by an out-of-sync detection circuit 104 on the basis of two clocks driving the buffers 101 and 103. Further, an amount of jitter between the two clocks driving the respective buffers 101 and 103 is detected by a jitter detection circuit 105 and the amount of interpolation data is controlled in the data interpolation circuit 106 on the basis of the amount of jitter.