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Lightly doped drain formation integrated with source/drain formation for high-performance transistor formation
Lightly doped drain formation integrated with source/drain formation for high-performance transistor formation
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机译:轻掺杂漏极结构与源/漏极结构集成在一起,可实现高性能晶体管
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摘要
An integrated circuit fabrication process is provided for forming a transistor in which the source/drain areas are formed simultaneously with the lightly doped drain areas. A gate electrode including a high-K gate dielectric and a gate conductor is formed upon a semiconductor substrate. The high-K gate dielectric is then selectively narrowed relative to the gate conductor. The source/drain areas and lightly doped drain areas are formed using a single impurity implant without the need for sidewall spacers on the gate electrode. A metal silicide layer may be formed across upper surfaces of the gate conductor and source/drain areas, also without the need for sidewall spacers on the gate electrode.
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