Output circuit which switches an output state in accordance with a timing signal and a delay signal of the timing signal

摘要

An output circuit according to the present invention is provided with a delay circuit for delaying an enable control signal by a predetermined period td and an output means capable of controlling the output state in either an enable or a disable state, wherein the output state of the first output means so controlled as to be switched from the disable to the enable in accordance with the enable control signal and to be switched from the enable to the disable state gradually in accordance with the signal supplied from the first delay circuit.