Digital integrated circuit with built-in timing delay circuit for e.g. autorefresh DRAM, has regulatable current source in timing circuit to produce output signal with a delay with respect to reference timing

摘要

The timing circuit (2) is connected to a selection circuit (3) that provides a control signal (TM). A regulatable current source (4) in the timing circuit receives the control signal producing a timing output signal (ST) with a delay with respect to a reference time. An Independent claim is also included for method of producing an output signal in timing circuit.