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Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control
Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control
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机译:基于监视和解码处理器总线周期的分层缓存系统刷新方案,用于刷新/清除序列控制
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摘要
An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.
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