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Method for making asymmetrical gate oxide thickness in channel MOSFET region

机译:沟道MOSFET区中不对称栅氧化层厚度的制作方法

摘要

A semiconductor device has gate with a first material having a first dielectric constant adjacent the semiconductor substrate and a second material having a second dielectric constant adjacent the semiconductor substrate. A conductor, such as polysilicon, is then placed on the gate so that the first and second materials are sandwiched between the conductor and the semiconductor substrate. Since the dielectric constants of the two materials are different, the gate acts like a gate having a single dielectric with at least two thicknesses. One dielectric constant is larger than the other dielectric constant. The higher dielectric constant material is comprised of a single spacer located within the gate at the sidewall nearest the drain of the semiconductor device. A layer of silicon dioxide is positioned on the semiconductor substrate between the spacer and the other sidewall of the gate. The thickness of the spacers can be adjusted to optimize the performance of the semiconductor device.
机译:半导体器件具有栅极,该栅极具有在半导体衬底附近具有第一介电常数的第一材料和在半导体衬底附近具有第二介电常数的第二材料。然后将诸如多晶硅的导体置于栅极上,使得第一和第二材料被夹在导体与半导体衬底之间。由于两种材料的介电常数不同,因此栅极的作用类似于具有至少两种厚度的单一电介质的栅极。一个介电常数大于另一个介电常数。较高介电常数的材料由位于靠近半导体器件的漏极的侧壁处的栅极内的单个间隔物组成。二氧化硅层位于隔离物和栅极的另一侧壁之间的半导体衬底上。可以调节间隔物的厚度以优化半导体器件的性能。

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