首页> 外国专利> Method and apparatus for cache line prediction and prefetching using a prefetch controller and buffer and access history

Method and apparatus for cache line prediction and prefetching using a prefetch controller and buffer and access history

机译:使用预取控制器以及缓冲区和访问历史记录进行高速缓存行预测和预取的方法和装置

摘要

A microprocessor includes an execution engine, a prediction table cache, and a prefetch controller. The execution engine is adapted to issue a memory request. The memory request includes an identifier corresponding to a row location in an external main memory. The prediction table cache is adapted to store a plurality of entries defining an access history of previously encountered memory requests. The prediction table cache is indexed by the identifier. The prefetch controller is adapted to receive the memory request and generate at least one prefetch candidate based on the memory request and the access history. A method for prefetching data in a microprocessor includes receiving a memory request. The memory request includes an identifier corresponding to a row location in an external main memory. The memory request is compared to an access history of previously encountered memory requests. The access history is indexed by the identifier. At least one prefetch candidate is generated based on the memory request and the access history.
机译:微处理器包括执行引擎,预测表高速缓存和预取控制器。执行引擎适于发出存储请求。存储器请求包括与外部主存储器中的行位置相对应的标识符。预测表高速缓存适于存储定义先前遇到的存储器请求的访问历史的多个条目。预测表缓存由标识符索引。预取控制器适于接收存储器请求并基于存储器请求和访问历史生成至少一个预取候选。在微处理器中预取数据的方法包括接收存储器请求。存储器请求包括与外部主存储器中的行位置相对应的标识符。将内存请求与先前遇到的内存请求的访问历史进行比较。访问历史由标识符索引。基于存储器请求和访问历史生成至少一个预取候选。

著录项

  • 公开/公告号US6134643A

    专利类型

  • 公开/公告日2000-10-17

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US19970979575

  • 发明设计人 RONNY RONEN;ADI YOAZ;GERSHON KEDEM;

    申请日1997-11-26

  • 分类号G06F12/08;

  • 国家 US

  • 入库时间 2022-08-22 01:35:54

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