The phase lock looping which possesses the instantaneous conservation output where the phase lock looping is locked is released

摘要

(57) Abstract While PLL being locked and being released the circuit which it controls or adjusts phase lock looping (PLL), or is offered. With the noise on the input signal of PLL or breaking of the data, there are times when PLL output frequency augments suddenly, matches input signal frequency. With many examples, noise and it is not possible with the low-pass filter inside PLL to remove the data which is broken. The input signal is received, in order to decide the time when removal impossible noise is generated, the detector is joined. As for this detector it is possible, to include the decoder, as for the decoder, for example, it decodes error amendment coding inside the input signal data stream, it shows the instant where PLL is locked is released. The detector shows lock release condition, when the lock release selection signal is transferred to the multiplexer, as for the multiplexer, it is not the PLL output clock pulse and the frequency dividing clock pulse is chosen. Succession the frequency dividing clock pulse, at the speed which the digital processor accepts, the PLL output clock pulse in lock release state is not accepted vis-a-vis that. Therefore, as for the digital processor, when the PLL clock pulse exceeds processor maximum operating frequency, it is possible to maintain working condition.