High frequency clock signal distribution circuit with reduced clock skew

摘要

A clock signal distribution circuit of a tree structure having a plurality of buffers (101-144;301-344) arranged in a plurality of hierarchal stages includes short-circuit wirings (161-164,171-194;361-364,371-394) for short-circuiting output terminals of the buffers at each stage of the plurality of hierarchal stages. Each of the plurality of buffers is formed by a single inverter or a multi-stage inverter wherein an input stage inverter (351) and an output stage inverter (352) are connected in series. The output stage inverter (352) has a size larger than that of the input stage inverter (351). The clock signal distribution circuit thus constructed can reduce clock skew and distribute a high frequency clock signal having sharp rise and fall characteristics to a plurality of registers. IMAGE IMAGE