The clock supply in large-scale systems with synchronous digital signal processing, for example in an SDH switching distributor, is designed as redundant in order to prevent operational system failure in the event of local failures or interruptions. The problem lies in completing the transition, without interference, from the defective clock pulse train to a different equivalent clock pulse train which has a different phase relation. A phase-locked loop generates the pulse train which is to be output. The phase shift is prevented by a changeover within the phase-locked loop, more precisely the control voltage of the PLL, in conjunction with a plurality of phase-shift compensation circuits (33, 34), one of which in each case constitutes the first part of the PLL. The phase-shift compensation circuit (33, 34) essentially comprises the phase discriminator of the PLL, supplemented by an adjustable delay and a correction voltage which can be readjusted. If the circuit is inserted in the PLL, the delay and the correction voltage remain set at the last determined value. The changeover is carried out in a virtually floating manner and essentially without phase change and without a transient effect. A frame insertion circuit (41) together with a frame monitor in the phase-shift compensation circuit enable the phase-exact processing of modulated clock pulse trains and open-circuit operation if all clock presettings fail. IMAGE
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