DC OFFSET COMPENSATION AND BIT TIMING SYNCHRONISATION USING CORRELATIONS WITH K NOWN BIT PATTERNS

摘要

An offset estimation and bit timing system and method. The inventive offset estimation system includes a first circuit for receiving and correlating a transmitted signal and generating a trigger signal in response thereto. A second circuit accumulates the received signal and provides a second signal on receipt of the trigger signal. The second signal is then converted to an offset error signal. In an illustrative implementation, the offset estimation system is implemented in a Bluetooth-enabled wireless receiver adapted to receive a signal transmitted with a known bit pattern. The received signal includes a plurality of messages, each message having at least one access code and each access code having a predetermined pattern therein for at least a portion thereof. The offset estimation system analyses the bit pattern and detects the DC offset in the received signal. The error signal is converted to analog and used as a reference input for the A/D converter. As an alternative, the error signal may be used to adjust the signal output by an intermediate frequency downconversion stage. The novel bit timing system includes a first circuit for receiving and correlating the first signal with a set of weights and providing a correlated signal in response thereto. The weights are chosen to achieve the highest correlation with respect to the predetermined bit pattern in the transmitted signal. A second circuit is included for identifying a peak in the correlated signal and providing a bit timing output signal in response thereto. The bit timing output signal is then used by a data bit sampler for sampling data in the first signal.