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DC OFFSET COMPENSATION AND BIT TIMING SYNCHRONIZATION USING CORRELATIONS WITH KNOWN BIT PATTERNS
DC OFFSET COMPENSATION AND BIT TIMING SYNCHRONIZATION USING CORRELATIONS WITH KNOWN BIT PATTERNS
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机译:利用已知位模式的相关性进行直流偏移补偿和位定时同步
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摘要
An offset estimation and bit timing system and method configured to detect a DC offset in a received signal is disclosed herein. The inventive system includes a first circuit for receiving and correlating a transmitted signal and generating a trigger signal in response thereto. A second circuit accumulates the received signal and provides a second signal on receipt of the trigger signal. The second signal is then converted to an offset error signal. The error signal is converted to analog and used as a reference input for an A/D converter. As an alternative, the error signal may be used to adjust the signal output by an intermediate frequency downconversion stage.
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