首页> 外国专利> METHOD FOR INCREASING THE VERY-LARGE-SCALE-INTEGRATED VLSI CAPACITOR SIZE ON BULK SILICON AND SILICON-ON-INSULATOR SOI WAFERS AND STRUCTURE FORMED THEREBY

METHOD FOR INCREASING THE VERY-LARGE-SCALE-INTEGRATED VLSI CAPACITOR SIZE ON BULK SILICON AND SILICON-ON-INSULATOR SOI WAFERS AND STRUCTURE FORMED THEREBY

机译:散装硅和绝缘硅上硅片上超大型集成的VLSI电容器尺寸的增大方法及其结构

摘要

PURPOSE: A method for manufacturing a semiconductor device is provided to form an inexpensive capacitor without additional cost, and to increase the density of the capacitor by increasing a ratio of a silicon width to an interval between adjacent islands so that a sub-lithography characteristic is patterned. CONSTITUTION: At least one conductive island having a predetermined sidewall angle in a conductive substrate is formed. A dielectric material is formed on at least one conductive island. A conductive material is formed on the dielectric material. A contact between the conductive material and at least one conductive island is formed.
机译:目的:提供一种用于制造半导体器件的方法,以形成廉价的电容器而无需额外的成本,并且通过增加硅宽度与相邻岛之间的间隔的比率来增加电容器的密度,从而获得亚光刻特性。图案化。组成:在导电基板中形成至少一个具有预定侧壁角的导电岛。在至少一个导电岛上形成介电材料。在介电材料上形成导电材料。在导电材料和至少一个导电岛之间形成接触。

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