PROGRAMMABLE MEMORY TESTING DEVICE USING FIELD PROGRAMMABLE GATE ARRAYS

摘要

PURPOSE: A testing device of a semiconductor memory device is provided to test a memory through various testing vectors although the area of a chip comprising of a memory intend to test is reduced. CONSTITUTION: The testing device includes a testing logic(210), an inputting portion(220), an inputting register(230), an outputting register(250) and an outputting portion(260). The testing logic is positioned at the outside of a chip, generates a shift clock signal, which is a test inputting data and a controlling signal, a shift enabling signal, an input enabling signal and an output enabling signal in response to a test enabling signal and applies to a chip and inspects operation through the comparison of the test input data and a test output data in a memory. The inputting portion generates a large number of input signals inputted to the memory in response to signals inputted from the outside in a normal mode. The inputting register respectively transmits the large number of inputting signals to the memory as a large number of memory input signals in a normal mode and transforms the test inputting data applied as a series data in the test logic into a parallel data and then transmits to the memory as the large number of memory inputting signals in a testing mode, in response to the shift clock signal, the shift enabling signal and the input enabling signal. The outputting register transmits to the test logic as the test outputting data to transform a large number of memory outputting signals outputted in parallel from the memory into a series in the testing mode and transmits the large number of memory outputting signals to the outputting portion as a large number of outputting signals in the normal mode in response to the shift clock signal, the shift enabling signal and the input enabling signal. The outputting portion outputs the large number of outputting signals inputted through the memory in the normal mode to the outside.