ADDRESS GENERATOR FOR HERMITIAN SYMMETRIC DATA

摘要

PURPOSE: An address generator for Hermitian symmetric data is provided to reduce the size of a hardware, and to reduce the process time by generating an address in case that Hermitian symmetric data are generated. CONSTITUTION: A Hermitian symmetric address generator is equipped with a preliminary address generation unit(32) and an address generation unit(34). The preliminary address generation unit(32) generates a preliminary address(ADDR1) increased at intervals of two clocks. The address generator(34) receives the preliminary address, and generates an address(ADDR2) every clock. The preliminary address generation unit(32) is equipped with an adder(322) which adds an increasing constant to the preliminary address and generates an increasing address(IA), the first multiplexer(324) which selects and outputs one among the addresses according to the first control signal(S1) and the first register(326) which receives a signal outputted from the first multiplexer(324). The address generation unit(34) is equipped with a normal unit(341) which generates a normal address(NA), a maintenance unit(342) which generates a conjugation address(CA), the second multiplexer(344) which selects and outputs one among the addresses and the second register(346) which receives an output signal of the second multiplexer(344).