Phase locked loop for stable clock reproduction in applications of wide band channel clock recovery and method thereof

摘要

PURPOSE: A PLL(Phase Locked Loop) for regenerating a stable clock in a recovering process of a broadband channel clock and a method for operating the same are provided to regenerate a stable clock for a static phase error when an optic system is operated in constant angular velocity. CONSTITUTION: A charge pump(140) outputs a sourcing current result or a sinking current result by sourcing or sinking a current according to a frequency and a detected phase. The first low pass filter(150) performs low pass filtering for the output signal from the charge pump(140) and outputs the filtered result as a control voltage for direct current. The voltage controlled oscillator(170) converts the control voltage and predetermined reference voltage to the current and generates a PLL clock signal by delaying an oscillating output signal according to the amount of the converted current. A static phase error controller(160) changes the reference voltage by comparing the control voltage with a triangular signal.