Phase locked loop for stable clock reproduction in applications of wide band channel clock recovery and method thereof

摘要

The phase locked loop and method are disclosed for his behavior broadband channel clock restore stable clock reproduction. The present invention relates to a phase locked loop to input PLL clock signal and the EFM signal frequency, and phase detection and, by adjusting the amount of current by the frequency and phase detected result generates a PLL clock signal synchronized with the EFM signal. The phase locked loop of the present invention is provided with a charge pump, a first low-pass filter, a voltage controlled oscillator and phase error control stop. Charge pump source or sink current in response to the frequency and phase detected result, and outputs the current sourcing or sinking result. First low-pass filter is a low-pass filtered signal that is output from the charge pump, and outputs the filtered result as a control voltage of the direct current. A voltage controlled oscillator and converts the first control voltage output from the low-pass filter, a predetermined reference voltage to each of the differential inputs to the current, in response to the converted amount of current by delaying the oscillation output signal and generates a PLL clock signal. Stop phase error control unit controls the voltage and compares the triangular wave signal having a predetermined period and size, and changes the reference voltage corresponding to the comparison result. ; According to the phase-locked loop of the present invention, there is an effect that even if the PLL is a broadband channel clock recovery during the phase error still occurs, stable clock reproduction can be performed by maintaining constant the VCO control voltage.