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THREE DEVICE BICMOS GAIN CELL

机译:三种器件BICMOS增益单元

摘要

In accordance with the present invention, a non-destructive read three element BICMOS gain cell for a DRAM memory having two FETs and one bipolar element is disclosed. These gain cells have improved access time (reduced latency), can operate for longer periods of time before refresh operations are required, require less storage capacitance than conventional DRAM cells, and are lower than current manufacturing costs. It can be commercialized as. In a preferred embodiment 1, the gain cell comprises an n-channel metal oxide semiconductor field effect write transistor whose gate is connected to the write word line WLw. The drain of the write transistor is connected to a storage node Vs having an associated storage capacitance Cs, the source of which is connected to the write bit line BLw. The gate of the n-channel metal oxide semiconductor field effect read transistor is connected to the storage node Vs, the source of which is connected to the read word line WLr. The base of the PNP transistor is connected to the drain of the read transistor, and its emitter is connected to the read bit line BLr. Embodiment 2 consists of a p-channel FET and an NPN transistor.
机译:根据本发明,公开了一种用于具有两个FET和一个双极元件的DRAM存储器的非破坏性读取三元件BICMOS增益单元。这些增益单元具有改善的访问时间(减少了等待时间),可以在需要刷新操作之前运行更长的时间,比传统的DRAM单元需要更少的存储电容,并且低于当前的制造成本。它可以商业化为。在优选实施例1中,增益单元包括n沟道金属氧化物半导体场效应写晶体管,其栅极连接到写字线WLw。写入晶体管的漏极连接到具有关联的存储电容Cs的存储节点Vs,其源极连接到写入位线BLw。 n沟道金属氧化物半导体场效应读取晶体管的栅极连接到存储节点Vs,其源极连接到读取字线WLr。 PNP晶体管的基极连接到读取晶体管的漏极,并且其发射极连接到读取位线BLr。实施例2包括一个p沟道FET和一个NPN晶体管。

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