ARRANGEMENT FOR CONNECTING INTERSYSTEM PARALLEL BUS TO PERIPHERAL PARALLEL BUS INTERFACE

摘要

FIELD: computer engineering; data transmission among different parts of distributed computer systems. SUBSTANCE: arrangement has control units of driving and driven devices, interrupt and single-output-command shapers, registers of read-write address, driving and driven device write data, driving and driven device read data, random-access memory address, unmasked zones of peripheral parallel bus interface address, control, identifier, status, data-address multiplexers, read-only memory read-write address, check bit shaping units for driving and driven devices, read-only memory, control device, address comparison unit, intersystem parallel bus address decoder, interface, single command controller, and unibus signal transceivers. EFFECT: provision for device self-testing. 1 dwg