Circuit arrangement for the trouble-free initialization of delay-locked loop circuits with Fast-Lock

摘要

The circuit has a chip-internal clock synchronised to an external clock using a delay line driven via a phase detector, a filter, a counter and an ADC. The counter (5) consists of at least one higher value counter (9) and at least one lower value counter (8) driven by a counter clock signal and alternatively activated and deactivated with a control signal to reduce the time to regulate the DLL. The control signal is converted to a delayed control signal (fast del) that is held constant for a rising counter clock signal (clkcount) edge.