Wiring arrangement to prevent polarity reversion of DMOS transistor; has charge carrier area comprising individual spaced part-charge carrier areas which are electrically connected together

摘要

The arrangement has a charge carrier area (30) arranged in a drift area (14) of the transistor (10). The charge carrier area consists of individual spaced part-charge carrier areas (32), which are electrically connected together. The charge carrier edge has a charge carrier doping opposite the drain area and is supplied with a negative potential with respect to a drain connection (24) of the transistor.