Tuning method for signal delays on bus systems or networks between quick memory modules, involves selectively separating strip conductor run from certain capacitive load structures of printed circuit board

摘要

A test for signal delays on a bus system or network between memory modules (2) is performed. A strip conductor run (3-9) is selectively separated from certain capacitive load structures of a printed circuit board (1) according to the test result to minimize occurrence of maximum signal delays. A strip conductor run (3-9) of a bus system to network is provided to each printed circuit board (1) with capacitive load structures such that the strip conductor run is near the housing of a memory module (2). Independent claims are also included for the following: (a) a signal tuning device; (b) a memory assembly.