Circuit arrangement for discharging a capacitance charged to a high voltage to a low voltage controlled by means of a control unit

摘要

The aim of the invention is to discharge a first capacitor (CH) from a high voltage (VH) to a low voltage (VL). To this end, the one electrode of the first capacitor (CH) is linked with the one electrode of a second capacitor (CL) via a FET (P1) path. The other two electrodes of the two capacitors (CH, CL) are applied to a reference potential. A voltage source (UL) with its internal resistance (RL) is disposed in parallel to the second capacitor (CL). A discharge path leads from the one electrode of the first capacitor (CH) from the paths of two FET (P2, M1) and a protective resistor (R) to the reference potential. A current path leads from the one electrode of the second capacitor (CL) to the reference potential via the paths of two additional FET (P3, M2 or M3). A control unit (SE) switches on the discharge path. Once the voltage of the first capacity (CH) has decreased to the required lower value (VL), the discharge path is blocked while a holding path is opened.