A method for fan-out of electronic components for the design or layout of circuit boards, in which the design or layout is computed according to: a = ps (1); b = vp-ps-cmax (2); where cmax = c pc/2 with an even number of pins; and cmax = c (pc-1)/2 with an odd number of pins; c = (vv-pp) tan(asin(tt/vv) (3); x = cc(pc-1)/2 (4); where ps = spacing of terminals (7) to the edge of the SMD-pads (6); pc = number of pins (5) in a row; pp = spacing of the pins (5) from one another; vv = spacing of test points (2) to one another; vp = spacing of test points (2) from terminal (7); tt = spacing of circuit boards (4) from one another. The surface covered by the fan-out is minimized in dependence of the number of pins (pc), the spacing of the test points from the terminal (vp), and the spacing of the test points from one another (vv).
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机译:一种用于电子元件的扇出方法,用于电路板的设计或布局,其中根据以下公式计算设计或布局:a = ps(1); b = vp-ps-cmax(2);其中cmax = c pc / 2,引脚数为偶数;和cmax = c(pc-1)/ 2,引脚数为奇数; c =(vv-pp)tan(asin(tt / vv)(3); x = cc(pc-1)/ 2(4);其中ps =端子(7)与SMD焊盘边缘的间距(6); pc =连续的引脚数(5); pp =引脚(5)的间距; vv =测试点(2)彼此的间距; vp =测试点的间距(2 )到端子(7)的距离; tt =电路板(4)彼此的间距。取决于引脚数(pc),测试点与端子的间距,扇出所覆盖的表面最小化(vp),以及测试点之间的间距(vv)。
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