首页> 外国专利> Semiconductor device e.g., metal oxide semiconductor field effect transistor includes silicon on insulator substrate with semiconductor layer, isolation films, gate electrode, intermediate layer isolation film and filled contact hole

Semiconductor device e.g., metal oxide semiconductor field effect transistor includes silicon on insulator substrate with semiconductor layer, isolation films, gate electrode, intermediate layer isolation film and filled contact hole

机译:半导体器件,例如金属氧化物半导体场效应晶体管,包括绝缘体衬底上的硅,该绝缘体衬底上具有半导体层,隔离膜,栅电极,中间层隔离膜和填充的接触孔

摘要

Semiconductor device comprises: a silicon on insulator (SOI) substrate with a semiconductor layer; a first element isolation film and a gate isolation film on the semiconductor layer; a gate electrode formed on the gate isolation film and the element isolation film; an intermediate layer isolation film, and a contact hole filled with a conductor on the intermediate layer isolation film. Semiconductor device comprises: a silicon on insulator substrate (1) with a semiconductor substrate (2), an insulating layer (3) and a semiconductor layer (4); a first element isolation film (9) and a gate isolation film (5N) formed on the surface of the semiconductor layer; a gate electrode (6N) formed on the gate isolation film and the element isolation film; an intermediate layer isolation film (10) formed on the gate electrode and the first element isolation film; and a contact hole (11N) filled with a conductor (21) formed on the surface of the intermediate layer isolation film. The conductor is in contact with the gate electrode on the first element isolation film. An Independent claim is also included for a process for the production of the semiconductor device. Preferred Features: The gate electrode is formed so that its side wall lies on the first element isolation film. The conductor is in contact with the side wall of the gate electrode.
机译:半导体器件包括:具有半导体层的绝缘体上硅(SOI)衬底;以及绝缘层。半导体层上的第一元件隔离膜和栅极隔离膜;在栅极隔离膜和元件隔离膜上形成的栅电极;中间层隔离膜,以及在中间层隔离膜上填充有导体的接触孔。半导体器件包括:绝缘体上的硅衬底(1),具有半导体衬底(2),绝缘层(3)和半导体层(4);在半导体层的表面上形成的第一元件隔离膜(9)和栅极隔离膜(5N)。在栅隔离膜和元件隔离膜上形成的栅电极(6N);形成在栅电极和第一元件隔离膜上的中间层隔离膜(10);接触孔(11N)填充有形成在中间层隔离膜的表面上的导体(21)。导体与第一元件隔离膜上的栅电极接触。对于半导体器件的制造方法,也包括独立权利要求。优选特征:形成栅电极,使得其侧壁位于第一元件隔离膜上。导体与栅电极的侧壁接触。

著录项

  • 公开/公告号DE10043183A1

    专利类型

  • 公开/公告日2001-04-12

    原文格式PDF

  • 申请/专利权人 MITSUBISHI DENKI K.K. TOKIO/TOKYO;

    申请/专利号DE2000143183

  • 发明设计人 HIRANO YUUICHI;

    申请日2000-09-01

  • 分类号H01L27/12;H01L21/84;H01L29/78;H01L27/088;

  • 国家 DE

  • 入库时间 2022-08-22 01:09:43

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