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SEMICONDUCTOR MEMORY DEVICE ALLOWING INCREASE IN CAPACITY AND OPERATION SPEED WITH A SUPPRESSED LAYOUT AREA
SEMICONDUCTOR MEMORY DEVICE ALLOWING INCREASE IN CAPACITY AND OPERATION SPEED WITH A SUPPRESSED LAYOUT AREA
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机译:半导体存储器的容量和操作速度得以提高,且布局面积得到了抑制
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摘要
A column select gate of a semiconductor memory device includes read gate circuits. Each read gate circuit includes read gate transistors. Each read gate transistor connects a read column select line to a global I/O line pair in response to a potential level on a bit line pair received on its gate and the potential on the read column select line. A voltage drop caused on one of the paired global I/O lines by turn-on of the read gate transistor is amplified by a main read amplifier to obtain read data.
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