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Combination test structures for in-situ measurements during fabrication of semiconductor devices
Combination test structures for in-situ measurements during fabrication of semiconductor devices
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机译:半导体器件制造过程中用于现场测量的组合测试结构
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摘要
A first test structure (40) is used to measure both the gate resistance/linewidth and transistor performance. A gate line (42) crosses a moat region (44) with source (48) and drain (50) regions formed on either side of the gate line (42). The gate line (42) is connected to four probe pads (52) in an H configuration for accurate linewidth measurements. A second test structure (70) may be used alone or in conjunction with the first test structure. A single gate line (72) crosses a moat region (74) several times. This allows both capacitance and gate gate-resistance measurements with the same test structure and for more accurate TLD measurement.
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