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Method and system for determining critical area for circuit layouts using voronoi diagrams
Method and system for determining critical area for circuit layouts using voronoi diagrams
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机译:使用伏洛诺伊图确定电路布局的关键区域的方法和系统
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摘要
A method for computing critical area for shorts of a layout, in accordance with the present invention, includes the steps of computing a Voronoi diagram for the layout, computing a second order Voronoi diagram to arrive at a partitioning of the layout into regions, computing critical area within each region and summing the critical areas to arrive at a total critical area for shorts in the layout. A system is also provided for calculating the critical area.
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