Method of design for testability at RTL and integrated circuit designed by the same

摘要

The invention provides a method of design for testability in which design of an integrated circuit is modified, at a register transfer level (RTL) with high abstraction than the gate level, so as to be simply testable and in which the area of a test circuit and the number of test patterns can be decreased as compared with those in the conventional method. An integrated circuit which has been designed in an RTL design step is partitioned into blocks each satisfying a previously defined simply testable condition in a partitioning step, so that the integrated circuit can be simply tested after manufacture. The simply testable condition can be that a circuit has an acyclic structure including no feedback loop, that a circuit has an n-fold line-up structure (wherein n is a positive integer), or the like. In the integrated circuit having been partitioned into the blocks in the partitioning step, the design is modified by using multiplexers, isolation controllers and the like in an isolation step so that the respective blocks can be independently tested.