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Low side current sink circuit having improved output impedance to reduce effects of leakage current
Low side current sink circuit having improved output impedance to reduce effects of leakage current
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机译:低侧电流吸收器电路,具有改进的输出阻抗,可减少漏电流的影响
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摘要
A low side, low voltage current sink circuit having improved output impedance to reduce effects of leakage current. A current sink circuit is described having a transistor having its emitter coupled to an emitter degeneration resistor which is coupled to the low side (e.g., ground) of a power supply. The output of the current sink is taken at the collector of the transistor. In one embodiment, the transistor is an NPN transistor device. The base of the transistor is coupled to the output of an operational amplifier. One input of the operational amplifier is coupled in a feedback loop to the emitter of the transistor. A direct current bias voltage is applied to the other input of the operational amplifier. In this arrangement, the output impedance (R″o) of the current is sink is based on the open loop gain of the operational amplifier (e.g., about 35 dB) and is therefore orders of magnitude larger than the output impedance of other prior art current sink designs. The novel design limits the voltage drop over the emitter degeneration resistor thereby increasing the differential voltage swing at the collector of the transistor for low power applications. The present invention finds particular application within a clock generator circuit where its reduced leakage current properties and improved dynamic range help to reduce clock jitter in the clock generation circuit.
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