Circuit for performing high-speed, low latency frame relay switching with support for fragmentation and reassembly and channel multiplexing

摘要

The present invention is a hardware implementation of frame relay switching functions which provides for real time concurrent multiple processes by implementing the processes in dedicated hardware logic operating in parallel, whereas in a typical software implementation the processes are sequentially processed. While data structures in software based implementations are accessed on some multiple of a byte regardless of the logical structure of the data, in the hardware implementation of the present invention the physical widths and the logical widths of the data structure elements are identical. This allows direct access of the logical structure by the operating process.