Asynchronous semiconductor memory device with a control circuit that controls the latch timing of an input signal

摘要

A semiconductor memory device 10 which includes an input part 11 to which an first external input signal CLK is input, an second input part 12 to which an second external input signal A0 is input, a latch signal generating part 14 which generates a latch signal LAT in response to the first external input signal CLK, an an output part 15 which latches the second external input signal A0 in response to the latch signal LAT and outputs the input signal to outside of the control circuit, is characterized in that it is provided with an inhibiting signal generating part 13 generating an inhibiting signal ST1, which is input to the latch signal generating part in response to the first external input signal CLK and the other input signal A0 to inhibit generation of the latch signal.