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Method for reducing surface charge on semiconductor wafers to prevent arcing during plasma deposition

机译:减少半导体晶片上表面电荷以防止在等离子体沉积过程中产生电弧的方法

摘要

A process of forming a layer of conductive material over a layer of insulating material is provided. A wafer is positioned on a wafer platform such that it is thermally and electrically coupled to the wafer platform. A clamping ring engages the peripheral edge of the wafer such that the wafer is held against the top surface of the wafer platform. The clamping ring is electrically coupled to the wafer pedestal. The wafer is exposed to a plasma comprising conductive material and an initial layer of conductive material is formed over the insulating layer until the top surface of the wafer is electrically coupled to the clamping ring. The wafer pedestal is then electrically biased and additional conductive material is formed. Once the initial layer of conductive material is electrically coupled to the clamping ring, the potential difference between the top and bottom surface of the wafer is zero such that arcing through the wafer is reduced. The wafer platform may also be exposed to the plasma so as to reduce the potential difference between the top and bottom surfaces of the wafer when the wafer platform is electrically biased.
机译:提供了一种在绝缘材料层上形成导电材料层的工艺。将晶片放置在晶片平台上,使得其热和电耦合至晶片平台。夹紧环接合晶片的外围边缘,使得晶片被保持抵靠晶片平台的顶表面。夹紧环电连接到晶片基座。晶片暴露于包含导电材料的等离子体中,并且在绝缘层上方形成导电材料的初始层,直到晶片的顶表面电耦合到夹持环。然后将晶片基座电偏置,并形成其他导电材料。一旦将导电材料的初始层电耦合到夹持环,晶片的顶表面和底表面之间的电势差为零,从而减少了通过晶片的电弧。晶片平台也可以暴露于等离子体,以减小当晶片平台被电偏置时晶片的顶表面和底表面之间的电势差。

著录项

  • 公开/公告号US6258718B1

    专利类型

  • 公开/公告日2001-07-10

    原文格式PDF

  • 申请/专利权人 MICRON TECHNOLOGY INC.;

    申请/专利号US20000482671

  • 发明设计人 SHANE P. LEIPHART;RANDLE D. BURTON;

    申请日2000-01-13

  • 分类号H01L214/40;

  • 国家 US

  • 入库时间 2022-08-22 01:03:53

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