Clock multiplier circuit capable of generating a high frequency clock signal from a low frequency input clock signal

摘要

A clock multiplier circuit comprises: a counter for counting the number of pulses of a predetermined output clock signal; an expected value generating circuit for generating an expected value for the number of pulses of the predetermined output clock signal per a first period which is sufficiently longer than one period of the predetermined output clock signal; a comparator circuit for comparing the counted value of the counter with the expected value per the first period to output a comparative information on the comparative resu a delay control circuit for generating a delay control signal indicative of change of the frequency of the predetermined output signal in accordance with the comparative information; and an output clock signal generating circuit for generating the predetermined output clock signal while changing the frequency in accordance with the delay control signal.