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Circuit with ramp-up control for overcoming a threshold voltage loss in an NMOS transistor
Circuit with ramp-up control for overcoming a threshold voltage loss in an NMOS transistor
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机译:具有斜升控制的电路可克服NMOS晶体管中的阈值电压损耗
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摘要
A ramping circuit gradually applies an erasing voltage to a memory cell. Within the ramping circuit an NMOS transistor is disclosed which gradually supplies the erasing voltage to the memory cell in response to an external ramping voltage. The NMOS transistor supplies the erasing voltage until the loss voltage of the transistor limits a maximum erasing voltage that the NMOS transistor can supply. The specification then discloses a PMOS transistor which operates to supply the erasing voltage to the memory cell when the NMOS transistor can no longer do so. The PMOS transistor is connected to control circuitry which keeps the PMOS transistor inactive until the output voltage of the NMOS transistor is limited by its voltage loss.
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